The present invention generally relates to semiconductor processes and structures, and more particularly, to a non-volatile memory compatible with logic devices and a fabrication method for the same.
With the rapid development of semiconductor techniques, system-on-chip (SOC) products are widely used in daily routines and improve the quality of life. Generally, the SOC consists of logic devices and non-volatile memory (NVM). The non-volatile memory is always embedded into the logic devices.
Traditionally, as the non-volatile memory needs to be embedded into the logic devices, one method is using multiple transistors connected to form a single polysilicon non-volatile memory. Such a method has poor density due to large cell size of the NVM. The other method is combined logic device processes and non-volatile memory processes. However, since at least two polysilicon layers need to be deposited, the processes are both too complex and demonstrate high overall manufacturing costs.
Consequently, how to make the non-volatile memory compatible with the logic devices and to create a high-density of the SOC so that both the non-volatile memory and the logic devices are optimized is currently a main issue for semiconductor manufacturers.
One object of the present invention is to utilize a non-volatile memory compatible with logic devices so that the non-volatile memory is easily embedded into the logic device processes.
A further object of the present invention is to use a non-volatile memory compatible with logic devices so that the non-volatile memory is rapidly programmed by a hot carrier effect induced from impact ionization.
Another object of the present invention is to use a non-volatile memory compatible with logic devices so that the hot carrier effect of the drain is further enhanced to increase impact ionization by the proposed device structure.
According to the above objects, the present invention sets forth a non-volatile memory compatible with logic devices and methods. A substrate has a first active region and a second active region. Thereafter, a first dielectric layer is formed on the first active region and the second active region. A conductive layer is deposited on the first dielectric layer to form a first gate on the first active region and to form a second gate on the second active region, and then the first dielectric layer is partially exposed. A second dielectric layer is deposited on the first dielectric layer such that electrons can be trapped in the second dielectric layer.
A third dielectric layer is formed on the second dielectric layer. An anisotropic etching process is then performed to form spacers adjacent to the first gate and second gate. Finally, conducting an implantation and an annealing step can create a source/drain on the substrate adjoining the spacers to make the non-volatile memory compatible with the logic devices.
Processes of fabricating logic devices allow the non-volatile devices in the first active region to be embedded so that the non-volatile memory is more preferably compatible with the logic devices. Due to the fact that the hot carrier effect occurs near the drain of the first active region, many electrons trapped in the second dielectric layer under the spacers are able to maintain the programming state of the non-volatile memory. Specifically, since a drain electrical field is imposed along the channel region in the first active region, an impact ionization of the hot (high energy) electrons occurs and then a portion of electrons are attracted to the second dielectric layer near the drain side by the gate electric field. Drain current of the programmed transistor will decrease due to higher serial resistance near the drain. The drain current of the programmed transistor will decrease further if the source and the drain are interchanged.
Performing the pocket implantation before forming the spacers preferably generates a higher electrical field near the drain to increase electron impact ionization thus electron-trapping occurs in the second dielectric layer under the spacers. Further, the fact that a LDD (Lightly Doped Drain) formed on the first active region forms a depletion region under the spacers will enhance electron impact ionization rate. When the first gate of the first active region turns on, more electrons are trapped in the second dielectric layer by the hot carrier effect to increase the programming efficiency of the non-volatile memory. In addition, because the electrons will only be trapped in the second dielectric layer near the drain side, if the source and the drain are interchanged, each proposed non-volatile memory cell can store two bits by the electron trapped in the second dielectric layer near both the drain and the source. Because the electrons trapped near the source side during a reading operation will reduce more drain current than that near the drain side, the stored two bits can be read out separately.
In summary, a non-volatile memory compatible with logic devices is provided in the present invention. A great number of electrons are trapped in the second dielectric layer by the hot carrier effect. In addition, two-bit data stored in the second dielectric layer under the spacers are easily read leading to high storage density of the non-volatile memory. More importantly, standard logic device processes are applied to embed the non-volatile memory into the logic devices so that the compatibility of the non-volatile memory and logic devices is readily met for a preferred scalability.